View LTC3676-15_8625355.PDF datasheet online --- IC-ON-LINE

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1 for more information www.linear.com/ltc3676 typical a pplica t ion fea t ures descrip t ion power management solution for application pr ocessors the lt c ? 3676 is a complete power management solution for advanced portable application processor-based sys- tems. the device contains four synchronous step-down dc/dc converters for core, memory, i/o, and system on-chip ( soc) rails and three 300 ma ldo regulators for low noise analog supplies. the ltc3676-1 has a 1.5a buck regulator configured to support ddr termination plus a vttr reference output. an i 2 c serial port is used to control regulator enables, power-down sequencing, output voltage levels, dynamic voltage scaling, operating modes and status reporting. regulator start-up is sequenced by connecting outputs to enable pins in the desired order or via the i 2 c port. system power-on, power-off and reset functions are controlled by pushbutton interface, pin inputs, or i 2 c. the ltc3676 supports i.mx, pxa and omap processors with eight independent rails at appropriate power levels. other features include interface signals such as the vstb pin that toggles between programmed run and standby output voltages on up to four rails simultaneously. the device is available in a 40- lead 6mm ? 6 mm qfn and 48 - lead exposed pad lqfp packages. start-up sequence a pplica t ions n quad i 2 c adjustable high efficiency step down dc/dc converters: 2.5a, 2.5a, 1.5a, 1.5a n three 300ma ldo regulators ( tw o adjustable) n ddr power solution with v tt and vttr reference n pushbutton on/off control with system reset n independent enable pin-strap or i 2 c sequencing n programmable autonomous power-down control n dynamic voltage scaling n power good and reset functions n selectable 2.25 mhz or 1.12 mhz switching frequency n always alive 25ma ldo regulator n 12a standby current n low profile 40-lead 6mm ? 6mm qfn and 48-lead exposed pad lqfp n supports freescale i.mx6, arm cortex, and other application processors n handheld instruments and scanners n portable industrial and medical devices n automotive infotainment n high end consumer devices n multi-rail systems l, lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 1f 47f v rtc 3v 25ma v arm 1.38v 2.5a ldo1 sw3 ltc3676-1 gnd v in 2.7v to 5.5v v in 1.5h 1f 47f v dd(high) 2.97v 300ma v soc 1.38v 1.5a ldo2 sw2 1.5h 1f 47f v ldo3 1.8v 300ma v ddr (v ddq ) 1.5v 2.5a ldo3 sw4 1.5h 1f 6 47f 3v 300ma v tt 1/2 v ddq 1.5a vttr (1/2 v ddq ) wake to processor 3676 ta01a ldo4 sw1 enables pwr_on on v ttr wake pgood i 2 c 1.5h 2 wake 1ms/div v dd(high) v arm and v soc v tt and v ttr v ldo3 v ddr 3676 ta01b 5v/div 1v/div 1v/div ltc 3676/ ltc 3676-1 3676fd
2 for more information www.linear.com/ltc3676 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in , dv dd , sw 1, sw 2, sw 3, sw4 ............... C 0.3 v to 6v sw 1, sw 2, sw 3, sw4 ( transient t < 1 s, duty cycle < 5%) ............... C2 v to 7v pv in 1 , pv in 2 , pv in 3 , pv in 4 , v in _l2 , v in _l3 , v in _l4 .................................. C0. 3 v to v in + 0.3 v ldo 1, fb _l 1, ldo 2, fb _l 2, ldo 3, ldo 4, fb _l 4, fb _b 1, fb _b 2, fb _b 3, fb _b 4, pgood , vstb , en _b 1, en _b 2, en _b 3, en _b 4, en _l 2, en _l 3, en _l 4, on , (note 1) wake , rsto , pwr _ on , irq , vttr , vddqin ....................................................... C 0.3 v to 6v sda , scl ...................................... C 0.3 v to dv dd + 0.3 v operating junction temperature range ( notes 2, 3) ............................................ C 40 c to 150 c storage temperature range ...................... C 65 to 150 c ltc3676 ltc3676-1 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 fb_l2 v in_l2 ldo2 ldo3 v in_l3 ldo4 v in_l4 fb_l4 en_l4 en_l3 en_l2 on ldo1 v in fb_l1 fb_b2 fb_b1 fb_b4 fb_b3 pwr_on sw1 pgood rsto en_b1 pv in1 pv in2 en_b2 wake irq sw2 sw4 dv dd sda scl pv in4 pv in3 en_b4 en_b3 vstb sw3 21 30 10 1 t jmax = 150c, u ja = 33c/w exposed pad ( pin 41) is gnd, must be soldered to pcb 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 gnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 fb_l2 v in_l2 ldo2 ldo3 v in_l3 ldo4 v in_l4 vddqin vttr en_l3 en_l2 on ldo1 v in fb_l1 fb_b2 fb_b1 fb_b4 fb_b3 pwr_on sw1 pgood rsto en_b1 pv in1 pv in2 en_b2 wake irq sw2 sw4 dv dd sda scl pv in4 pv in3 en_b4 en_b3 vstb sw3 21 30 10 1 t jmax = 150c, u ja = 33c/w exposed pad ( pin 41) is gnd, must be soldered to pcb ltc3676 ltc3676-1 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 nc fb_l2 v in_l2 ldo2 ldo3 v in_l3 ld04 v in_l4 fb_l4 en_l4 en_l3 nc 13 14 15 16 17 18 19 20 21 22 23 24 nc sw4 dv dd sda scl pv in4 pv in3 en_b4 en_b3 vstb sw3 nc 48 47 46 45 44 43 42 41 40 39 38 37 nc sw1 pgood rst0 en_b1 pv in1 pv in2 en_b2 wake irq sw2 nc nc en_l2 on ldo1 v in fb_l1 fb_b2 fb_b1 fb_b4 fb_b3 pwr_on nc top view lxe package 48-lead (7mm 7mm) plastic lqfp 49 gnd t jmax = 150c, u ja = 19c/w exposed pad ( pin 49) is gnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 nc fb_l2 v in_l2 ldo2 ldo3 v in_l3 ld04 v in_l4 vddqin vttr en_l3 nc 13 14 15 16 17 18 19 20 21 22 23 24 nc sw4 dv dd sda scl pv in4 pv in3 en_b4 en_b3 vstb sw3 nc 48 47 46 45 44 43 42 41 40 39 38 37 nc sw1 pgood rst0 en_b1 pv in1 pv in2 en_b2 wake irq sw2 nc nc en_l2 on ldo1 v in fb_l1 fb_b2 fb_b1 fb_b4 fb_b3 pwr_on nc top view lxe package 48-lead (7mm 7mm) plastic lqfp 49 gnd t jmax = 150c, u ja = 19c/w exposed pad ( pin 49) is gnd, must be soldered to pcb ltc 3676/ ltc 3676-1 3676fd
3 for more information www.linear.com/ltc3676 lead free finish tape and reel part marking* package description temperature range ltc3676euj#pbf ltc3676euj#trpbf ltc3676uj 40-lead (6mm ? 6mm) plastic qfn C40c to 125c ltc3676iuj#pbf ltc3676iuj#trpbf ltc3676uj 40-lead (6mm ? 6mm) plastic qfn C40c to 125c ltc3676huj#pbf ltc3676huj#trpbf ltc3676uj 40-lead (6mm ? 6mm) plastic qfn C40c to 150c ltc3676euj-1#pbf ltc3676euj-1#trpbf ltc3676uj-1 40-lead (6mm ? 6mm) plastic qfn C40c to 125c ltc3676iuj-1#pbf ltc3676iuj-1#trpbf ltc3676uj-1 40-lead (6mm ? 6mm) plastic qfn C40c to 125c ltc3676huj-1#pbf ltc3676huj-1#trpbf ltc3676uj-1 40-lead (6mm ? 6mm) plastic qfn C40c to 150c lead free finish tray part marking* package description temperature range ltc3676elxe#pbf ltc3676elxe#pbf ltc3676lxe 48-lead (7mm ? 7mm) plastic elqfp C40c to 125c ltc3676ilxe#pbf ltc3676ilxe#pbf ltc3676lxe 48-lead (7mm ? 7mm) plastic elqfp C40c to 125c ltc3676hlxe#pbf ltc3676hlxe#pbf ltc3676lxe 48-lead (7mm ? 7mm) plastic elqfp C40c to 150c ltc3676elxe-1#pbf ltc3676elxe-1#pbf ltc3676lxe-1 48-lead (7mm ? 7mm) plastic elqfp C40c to 125c ltc3676ilxe-1#pbf ltc3676ilxe-1#pbf ltc3676lxe-1 48-lead (7mm ? 7mm) plastic elqfp C40c to 125c ltc3676hlxe-1#pbf ltc3676hlxe-1#pbf ltc3676lxe-1 48-lead (7mm ? 7mm) plastic elqfp C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion ltc 3676/ ltc 3676-1 3676fd
4 for more information www.linear.com/ltc3676 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_l2 = v in_l3 = v in_l4 = dv dd = 3.8v. all regulators disabled unless otherwise noted. parameter conditions min typ max units operating input supply voltage, v in l 2.7 5.5 v v in standby current pwr_on = 0v l 12 21 a step-down switching regulators 1, 2, 3 and 4 output voltage range v fb pv in v burst mode ? v in quiescent current pulse-skipping mode v in quiescent current forced continuous v in quiescent current v fb = 850mv (note 5) v fb = 850mv (note 5) v fb = 0v (note 5) l l l 23 120 170 50 200 300 a a a feedback pin input current v fb = 850mv C0.05 0.05 a maximum duty cycle v fb = 0v 100 % sw pull-down resistance regulator disabled 625 feedback reference soft-start rate (note 6) 0.8 v/ms high feedback regulation voltage (v fb ) dvbxa[4:0] = dvbxb[4:0] = 11111, v in = 2.7v to 5.5v l 788 800 812 mv default feedback regulation voltage (v fb ) dvbxa[4:0] = dvbxb[4:0] = 11001, v in = 2.7v to 5.5v l 714 725 736 mv low feedback regulation voltage (v fb ) dvbxa[4:0] = dvbxb[4:0] = 00000, v in = 2.7v to 5.5v l 404 412.5 421 mv feedback lsb step size 12.5 mv switching frequency buckx[2] = 0 buckx[2] = 1 l l 1.7 0.85 2.25 1.125 2.7 1.35 mhz mhz 1.5 a step-down switching regulators 1 and 2 pmos current limit l 2 a pmos on-resistance (note 7) 160 m nmos on-resistance (note 7) 80 m 2.5a step-down switching regulators 3 and 4 pmos current limit l 3.0 a pmos on-resistance (note 7) 120 m nmos on-resistance (note 7) 70 m step-down switching regulator 1 and vttr ( ltc3676-1) buck 1 feedback regulation v oltage vddqin = 1.5v l vttr C 10 vttr vttr + 10 mv vttr output voltage vddqin = 1.5v l 0.49?vddqin 0.5?vddqin 0.51? vddqin mv vttr maximum output current l C10 10 ma i vin vttr enabled 1 ma ldo regulators 2, 3 and 4 feedback reference soft-start rate 10 v/ms output pull-down resistance regulator disabled 625 ldo regulator 1 output voltage range v fb_l1 v in feedback regulation voltage (v fb_l1 ) l 689 725 761 mv line regulation i ldo1 = 1ma, v ldo1 = 1.2v, v in = 2.7v to 5.5v 0.15 %/v load regulation i ldo1 = 0.1ma to 25ma, v ldo1 = 3.3v 0.1 % ltc 3676/ ltc 3676-1 3676fd
5 for more information www.linear.com/ltc3676 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_l2 = v in_l3 = v in_l4 = dv dd = 3.8v. all regulators disabled unless otherwise noted. parameter conditions min typ max units available output current l 25 ma short-circuit output current limit 65 100 ma dropout voltage (note 4) i ldo1 = 25ma, v ldo1 = 3.3v 200 280 mv feedback pin input current v fb_l1 = 850mv C0.05 0.05 a ldo regulator 2 v in_l2 input voltage l 1.7 v in v ldo2 output voltage range i ldo2 = 1ma v fb_l2 v in_l2 v available output current l 300 ma v in_l2 quiescent current v in_l2 shutdown current regulator enabled, i ldo2 = 0a regulator disabled l l 12 0 25 1 a a v in quiescent current regulator enabled l 50 85 a feedback regulation voltage (v fb_l2 ) l 0.707 0.725 0.743 v line regulation i ldo2 =1ma, v in = 2.7v to 5.5v 0.01 %/v load regulation i ldo2 = 1ma to 300ma 0.01 % short-circuit current limit 770 ma dropout voltage (note 4) i ldo2 = 300ma, v ldo2 = 2.5v i ldo2 = 300ma, v ldo2 = 1.2v 210 450 260 615 mv mv feedback pin input current v fb_l2 = 725mv C0.05 0.05 a ldo regulator 3 v in_l3 input voltage l 2.35 v in v output voltage v in_l3 = v in , i ldo3 = 1ma l 1.746 1.8 1.854 v available output current l 300 ma v in_l3 quiescent current v in_l3 shutdown current regulator enabled, i ldo3 = 0a regulator disabled l l 14 0 25 1 a a v in quiescent current regulator enabled l 50 85 a line regulation i ldo3 =1ma, v in = 2.7v to 5.5v 0.01 %/v load regulation i ldo3 = 1ma to 300ma 0.05 % short-circuit current limit 770 ma dropout voltage (note 4) i ldo3 = 300ma, v ldo3 = 1.8v 280 350 mv ldo regulator 4 v in_l4 input voltage l 1.7 v in v ldo4 output voltage range (ltc3676) i ldo4 = 1ma v fb_l4 v in_l4 v feedback regulation voltage (ltc3676) (v fb_l4 ) l 0.707 0.725 0.743 v output voltage (ltc3676-1) i ldo4 = 1ma, ldob[4:3] = 00 ldob[4:3] = 01 ldob[4:3] = 10 ldob[4:3] = 11 l l l l 1.164 2.425 2.716 2.91 1.2 2.5 2.8 3.0 1.236 2.575 2.884 3.09 v v v v available output current l 300 ma v in_l4 quiescent current v in_l4 shutdown current regulator enabled, i ldo4 = 0a regulator disabled l l 12 0 25 1 a a v in quiescent current regulator enabled l 50 85 a line regulation i ldo4 =1ma, v in = 2.7v to 5.5v 0.01 %/v ltc 3676/ ltc 3676-1 3676fd
6 for more information www.linear.com/ltc3676 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_l2 = v in_l3 = v in_l4 = dv dd = 3.8v. all regulators disabled unless otherwise noted. parameter conditions min typ max units load regulation (ltc3676) load regulation (ltc3676-1) i ldo4 = 1ma to 300ma 0.01 0.05 % % short -cir cuit current limit 770 ma dropout voltage (note 4) i ldo4 = 300ma, v ldo4 = 2.5v i ldo4 = 300ma, v ldo4 = 1.2v 210 450 260 615 mv mv feedback pin input current (ltc3676) v fb_l4 = 725mv C0.05 0.05 a enable inputs threshold rising all enables low l 0.75 1.2 v threshold falling one enable high l 0.4 0.7 precision threshold one or more enables l 0.370 0.400 0.430 v input pull-down resistance 4.5 m vstb, pwr_on inputs threshold l 0.370 0.400 0.430 v pull-down resistance 4.5 m pushbutton interface on threshold rising on threshold falling l l 0.4 0.75 0.7 1.2 v v on input current on = v in on = 0v C1 C40 1 a a on low t ime to irq low 50 ms on high time to irq high 0.2 s on low time to wake high 400 ms on low time to hard reset cntrl[6] = 0 10 sec irq minimum pulse width 50 ms irq blanking from wake low 1 sec minimum wake low time 1 sec wake high time with pwr_on = 0v 5 sec pwr_on high to wake high 3 ms pwr_on low to wake low 3 ms status output pins (wake, pgood, rsto, irq) wake output low voltage i wake = 3ma 0.1 0.4 v wake output high leakage current v wake = 3.8v C0.1 0.1 a pgood output low voltage i pgood = 3ma 0.1 0.4 v pgood output high leakage current v pgood = 3.8v C0.1 0.1 a pgood threshold rising pgood threshold falling C6 C8 % % rsto output low v oltage i rsto = 3ma 0.1 0.4 v rsto output high leakage current v rsto = 3.8v C0.1 0.1 a ldo1 power good threshold rising ldo1 power good threshold falling C7.5 C10 % % irq output low v oltage i irq = 3ma 0.1 0.4 v irq output high leakage current v irq = 3.8v C0.1 0.1 a ltc 3676/ ltc 3676-1 3676fd
7 for more information www.linear.com/ltc3676 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = pv in1 = pv in2 = pv in3 = pv in4 = v in_l2 = v in_l3 = v in_l4 = dv dd = 3.8v. all regulators disabled unless otherwise noted. parameter conditions min typ max units undervoltage lockout rising undervoltage lockout falling l l 2.35 2.55 2.45 2.65 v v under voltage w arning cntrl[4:2] = 000 (por default) cntrl[4:2] = 001 cntrl[4:2] = 010 cntrl[4:2] = 011 cntrl[4:2] = 100 cntrl[4:2] = 101 cntrl[4:2] = 110 cntrl[4:2] = 111 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 v v v v v v v v symbol parameter conditions min typ max units i 2 c port dv vdd dv dd input supply voltage l 1.6 5.5 v i dvdd dv dd quiescent current scl/sda = 0khz 0.3 1 a dv vdd_uvlo dv dd uvlo level 1 v address ltc3676 device address ltc3676-1 device address 0111100[ r/ w] 0111101[r/w] v ih sda/scl input threshold rising 70 %dv dd v il sda/scl input threshold falling 30 %dv dd i ih sda/scl high input current sda = scl = 5.5v C1 0 1 a i il sda/scl low input current sda = scl = 0v C1 0 1 a v ol_sda sda output low voltage i sda = 3ma 0.4 v f scl clock operating frequency 400 khz t buf bus free time between stop and start condition 1.3 s t hd_ sta hold time after repeated start condition 0.6 s t su_ sta repeated start condition setup time 0.6 s t su_sto stop condition setup time 0.6 s t hd_ dat (o) data hold time output 0 900 ns t hd_ dat (i) data hold time input 0 ns t su_ dat data setup time 100 ns t low scl clock low period 1.3 s t high scl clock high period 0.6 s t f clock/data fall time c b = capacitance of bus line (pf) 20 + 0.1c b 300 ns t r clock/data rise time c b = capacitance of bus line (pf) 20 + 0.1c b 300 ns t sp input spike suppression pulse width 50 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3676 is tested under pulsed load conditions such that t j t a . the ltc3676e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3676i is guaranteed over the C40c to 125c operating junction temperature range and the ltc3676h is guaranteed over the full C40c to 150c operating junction temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. the junction temperature (t j in c) is calculated from the ambient temperature (t a in c) and power dissipation (p d , in watts), and package to junction ambient thermal impedance (? j a in watts/c ) according to the formula: t j = t a + (p d ? ? j a ). note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. ltc 3676/ ltc 3676-1 3676fd
8 for more information www.linear.com/ltc3676 typical p er f or m ance c harac t eris t ics standby i vin vs v in ldo2 to ldo4 i vin vs v in step-down switching regulator i vin vs v in e lec t rical c harac t eris t ics note 3: the ltc3676 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 150c when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: dropout voltage is defined as (v in C v ldo1 ) for ldo1 or (v in_lx C v ldox ) for other ldos when v ldox is 3% lower than v ldox measured with v in = v in_lx = 4.3v. voltage (v) 2.5 i vin (a) 8 3676 g01 4 0 3.5 4.5 3.0 4.0 5.0 12 16 6 2 10 14 5.5 voltage (v) 2.5 0 i vin (a) 100 300 400 500 4.5 900 3676 g03 200 3.5 3.0 5.0 4.0 5.5 600 700 800 pulse-skipping mode enable four bucks enable three bucks enable two bucks enable one buck note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. note 6: soft-start measured in test mode with regulator error amplifier in unity-gain mode. note 7: the switching regulator pmos and nmos on-resistance is guaranteed by correlation to wafer level measurements. step-down switching regulator i vin vs v in input supply current vs temperature oscillator frequency vs temperature voltage (v) 2.5 0 i vin (a) 20 60 80 100 4.5 180 3676 g04 40 3.5 3.0 5.0 4.0 5.5 120 140 160 burst mode operation enable four bucks enable three bucks enable two bucks enable one buck v in = 3.8v, t a = 25c unless otherwise noted v in (v) 2.50 v in current (a) 100 150 3676 g02 50 0 3.50 4.50 5.50 250 200 enable 3 ldos enable 2 ldos enable 1 ldo temperature (c) ?50 0 v in current (a) 200 400 600 800 1000 1200 0 50 pulse-skipping standby burst mode operation 100 150 3676 g05 all regulators enabled temperature (c) ?50 2.00 frequency (mhz) 2.05 2.10 2.15 2.20 2.25 2.30 0 50 100 150 3676 g06 ltc 3676/ ltc 3676-1 3676fd
9 for more information www.linear.com/ltc3676 typical p er f or m ance c harac t eris t ics oscillator frequency change vs v in step-down switching regulators 1 and 2 efficiency vs i out step-down switching regulators 1 and 2 efficiency vs i out step-down switching regulators 3 and 4 efficiency vs i out buck r ds(on) vs temperature buck r ds(on) vs v in load current (ma) 1 0 efficieny (%) 20 30 40 50 60 70 10 100 3676 g08 80 90 100 burst 10 1000 pulse skipping forced continuous v in = 3.3v v out = 1.2v load current (ma) 1 0 efficieny (%) 20 30 40 50 60 70 10 100 3676 g09 80 90 100 burst 10 1000 pulse skipping forced continuous v in = 5v v out = 1.2v load current (ma) 1 0 efficieny (%) 20 30 40 50 60 v out = 2.5v 70 10 100 3676 g10 80 90 100 10 1000 v in = 3.3v pulse-skipping mode v out = 1.2v step-down switching regulator load step step-down switching regulator current limit vs temperature ltc3676-1 vddqin, vttr and v tt start-up pgood 5v/div vttr 1v/div vtt (buck1) 1v/div vddqin 1v/div 400s/div 3676 g14 100mv/div 500ma/div 10s/div c out = 44f 3676 g15 v out = 1.2v i load = 0.5a to 1.5a v in (v) 2.5 percent change (%) 0 3676 g07 ?0.4 ?0.8 3.5 4.5 3.0 4.0 5.0 0.4 0.8 ?0.2 ?0.6 0.2 0.6 5.5 temperature (c) ?50 r ds(on) (m) 100 150 150 3676 g11 50 0 0 50 100 250 200 buck 1, 2 pmos buck 1, 2 nmos buck 3, 4 nmos buck 3, 4 pmos v in (v) 2.5 0 r ds(on) (m) 20 60 80 100 200 140 3.5 4.5 3676 g12 40 160 180 120 5.5 buck 3, 4 pmos buck 1, 2 pmos buck 1, 2 nmos buck 3, 4 nmos temperature (c) ?50 1.5 current (a) 2.0 2.5 3.0 3.5 4.0 4.5 0 50 100 150 3676 g13 buck 3, 4 buck 1, 2 ltc 3676/ ltc 3676-1 3676fd
10 for more information www.linear.com/ltc3676 typical p er f or m ance c harac t eris t ics ltc3676-1 v tt load step ldo1 dropout voltage vs temperature ldo1 short-circuit current vs temperature 100mv/div 1a/div 40s/div c out = 88f 3676 g16 v tt = 0.75v i load = ?1.2a to 1.2a ltc3676-1 temperature (c) ?55 dropout voltage (mv) 200 250 300 150 3676 g17 150 100 0 0 50 100 50 400 350 v ldo1 = 1.8v i ldo1 = 25ma v ldo1 = 3.3v temperature (c) ?55 ldo1 short-circuit current (ma) 60 65 70 150 3676 g18 55 50 40 0 50 100 45 80 75 ldo2 to ldo4 load step response ldo1 load step response ldo2 to ldo4 dropout voltage vs temperature ldo2 to ldo4 short-circuit current vs temperature 50mv/div v ldo = 1.8v i load = 220ma 10ma 100ma/div 10s/div 3676 g22 v ldo1 50mv/div i ldo1 10ma/div 40s/div 3676 g19 1.2v 20ma 1ma temperature (c) ?50 dropout voltage (mv) 250 300 350 150 3676 g20 200 150 100 0 0 50 100 50 450 v ldo = 1.2v v ldo = 1.8v v ldo = 3.3v 400 i ldo = 200ma temperature (c) ?50 300 ldo short-circuit current (ma) 350 450 500 550 800 650 0 50 3676 g21 400 700 750 600 100 150 ltc 3676/ ltc 3676-1 3676fd
11 for more information www.linear.com/ltc3676 p in func t ions fb_l2 (pin 1/pin 2): feedback input for ldo2. set full- scale output voltage using a resistor divider connected from ldo2 to this pin to ground. v in_l2 ( pin 2/pin 3): power input for ldo2. this pin should be bypassed to ground with a 1 f or greater ceramic capacitor.voltage on v in_l2 should not exceed voltage on v in pin. ldo2 (pin 3/pin 4): output voltage of ldo2. nominal output voltage is set with a resistor feedback divider that servos to a fixed 725 mv reference. this pin must be by - passed to ground with a 1 f or greater ceramic capacitor. ldo 3 (pin 4/pin 5): output voltage of ldo3. nominal output voltage is a fixed 1.8 v. this pin must be bypassed to ground with a 1f or greater ceramic capacitor. v in_l3 ( pin 5/pin 6): power input for ldo3. this pin should be bypassed to ground with a 1 f or greater ceramic capacitor.voltage on v in_l3 should not exceed voltage on v in pin. ldo4 (pin 6/pin 7): output voltage of ldo4. nominal output voltage is set with a resistor feedback divider that servos to a fixed 725 mv reference. this pin must be by - passed to ground with a 1 f or greater ceramic capacitor. v in_l4 ( pin 7/pin 8): power input for ldo4. this pin should be bypassed to ground with a 1 f or greater ceramic capacitor.voltage on v in_l4 should not exceed voltage on v in pin. fb_l4 (pin 8/pin 9): feedback input for ltc3676 ldo4. set full-scale output voltage using a resistor divider con - nected from ldo4 to this pin to ground. vddqin ( pin 8/pin 9): v dd sense input for ltc3676-1. tie ddr memory v dd supply to this pin. en_l4 (pin 9/pin 10): enable ldo4 input for ltc3676. active high enables ldo4. a weak pull-down pulls en_l4 low when left floating. vttr (pin 9/pin 10): ddr v ref output pin for ltc3676 - 1. buffered reference equal to one-half vddqin voltage on pin 8. en_l 3 (pin 10/pin 11): enable ldo3 input. active high enables ldo3. a weak pull-down pulls en_l3 low when left floating. sw4 (pin 11/pin 14): switch pin for step-down switch - ing regulator 4. connect one side of step-down switching regulator 4 inductor to this pin. dv dd ( pin 12/pin 15): supply voltage for i 2 c serial port. this pin sets the logic reference level of scl and sda i 2 c pins. dv dd resets i 2 c registers to power-on state when driven to <1 v. scl and sda logic levels are scaled to dv dd . connect a 0.1 f decoupling capacitor from this pin to ground. sda (pin 13/pin 16): data pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv dd . scl (pin 14/pin 17): clock pin for the i 2 c serial port. the i 2 c logic levels are scaled with respect to dv dd . pv in4 ( pin 15/ pin 18): power input for step-down switch- ing regulator 4. tie this pin to v in supply. this pin should be bypassed to ground with a 10 f or greater ceramic capacitor. pv in3 ( pin 16/ pin 19): power input for step-down switch- ing regulator 3. tie this pin to the v in supply. this pin should be bypassed to ground with a 10 f or greater ceramic capacitor. en_b4 (pin 17/pin 20): enable step-down switching regulator?4. active high input enables step- down switching regulator?4. a weak pull-down pulls en_b4 low when left floating. en_b3 (pin 18//pin 21): enable step-down switching regulator?3. active high input enables step- down switching regulator?3. a weak pull-down pulls en_b3 low when left floating. vstb (pin 19/pin 22): voltage standby. when vstb is low, the dac registers are selected by command register bit dvbxa[5]. when vstb is high, the dac registers are forced to dvbxb registers. tie vstb to ground if unused. sw3 (pin 20/pin 23): switch pin for step-down switch - ing regulator 3. connect one side of step-down switching regulator?3 inductor to this pin. pwr_ on ( pin 21/pin 26): external power on. handshaking pin to acknowledge successful power - on sequence . pwr_on must be driven high within five seconds of wake going high to keep power on. pwr_on can be (qfn/lqfp) ltc 3676/ ltc 3676-1 3676fd
12 for more information www.linear.com/ltc3676 p in func t ions used to activate the wake output by driving high. drive low to shut down wake. fb_b 3 (pin 22/pin 27): feedback input for step-down switching regulator 3. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 3 to this pin to ground. fb_b 4 (pin 23/pin 28): feedback input for step-down switching regulator 4. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 4 to this pin to ground. fb_b 1 (pin 24/pin 29): feedback input for step-down switching regulator 1. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 1 to this pin to ground. fb_b 2 (pin 25/pin 30): feedback input for step-down switching regulator 2. set full-scale output voltage using resistor divider connected from the output of step-down switching regulator 2 to this pin to ground. fb_l1 (pin 26/pin 31): feedback input for ldo1. set output voltage using a resistor divider connected from ldo1 to this pin to ground. v in (pin 27/pin 32): supply voltage input. this pin should be bypassed to ground with a 1 f or greater ceramic capacitor. all switching regulator pv in supplies should be tied to v in . ldo1 (pin 28/pin 33): always on ldo1 output. this pin provides an always-on supply voltage useful for light loads such as a watchdog microprocessor or a real time clock. connect a 1f capacitor from ldo1 to ground. on (pin 29/pin 34): pushbutton input. a weak internal pull-up forces on high when left floating. a normally open pushbutton is connected from on to ground forcing a low state when pushed. en_l 2 (pin 30/pin 35): enable ldo2 input. active high enables ldo2. a weak pull-down pulls en_l2 low when left floating. sw2 (pin 31/pin 38): switch pin for step-down switch - ing regulator 2. connect one side of step-down switching regulator?2 inductor to this pin. irq ( pin 32/pin 39): interrupt request output. open - drain driver is pulled low for power good, undervoltage, and overtemperature warning and fault conditions. clear irq by writing to the i 2 c clirq command register. wake (pin 33/pin 40): system wake up. open-drain driver output releases high when signaled by pushbutton activation or pwr_on input. it may be used to initiate a pin-strapped power-up sequence by connecting to a regulator enable pin. en _b 2 ( pin 34/pin 41): enable step - down switching regulator? 2. active high input enables step- down switching regulator?2. a weak pull- down pulls en _b 2 low when left floating. pv in2 ( pin 35/ pin 42): power input for step-down switch- ing regulator 2. tie this pin to v in supply. this pin should be bypassed to ground with a 10 f or greater ceramic capacitor. pv in1 (pin 36/pin 43): power input for step- down switching regulator 1. tie this pin to v in supply. this pin should be bypassed to ground with a 10 f or greater ceramic capacitor. en_b1 (pin 37/pin 44): enable step-down switching regulator? 1. active high enables step-down switching regulator 1. the ltc3676-1 en_b1 pin enables both vttr output and switching regulator 1. a week pull-down pulls en_b1 low when left floating. rsto (pin 38/pin 45): reset output. open-drain output pulls low when the always-on regulator ldo1 is below regulation or during a hard reset initiated by a pushbutton input or command registers. pgood (pin 39/pin 46): power good output. open-drain output pulls low when any enabled regulator falls below power good threshold or during dynamic voltage slew unless disabled in command register. pulls low when all regulators are disabled. sw1 ( pin 40/pin 47): switch pin for step-down switch- ing regulator 1. connect one side of step-down switching regulator?1 inductor to this pin. gnd ( exposed pad pin 41/pin 49): ground. the exposed pad must be connected to a continuous ground plane of the printed circuit board by multiple interconnect vias directly under the ltc3676 to maximize electrical and thermal conduction. ltc 3676/ ltc 3676-1 3676fd
13 for more information www.linear.com/ltc3676 b lock diagra m l t c 3676 buck1 v ref en ok default = 725mv range = 800mv to 412.5mv pv in1 sw1 fb_b1 dac ldo1 en 725mv v in ldo1 fb_l1 buck2 v ref en ok default = 725mv range = 800mv to 412.5mv pv in2 sw2 fb_b2 dac buck3 v ref en ok default = 725mv range = 800mv to 412.5mv pv in3 sw3 fb_b3 dac buck4 ldo2 v ref en ok default = 725mv range = 800mv to 412.5mv precision enable threshold and sequence delay pv in4 sw4 v in_l2 ldo2 fb_b4 v ref 725mv en ok fb_l2 dac ldo4 v in_l4 ldo4 v ref en ok gnd (exposed pad) fb_l4 3676 bd ldo3 v in_l3 ldo3 v ref en ok en_b1 5 5 5 5 pushbutton on/off control on wake en_b2 en_b3 i 2 c command registers dv dd dynamic voltage scaling control fault detection under voltage over temperature sda scl vstb en_b4 en_l2 en_l3 en_l4 pwr_on rsto irq pgood vsel va 4x5 7 7 7 vb 4x5 ltc 3676/ ltc 3676-1 3676fd
14 for more information www.linear.com/ltc3676 b lock diagra m l t c 3676-1 buck1 v ref en ok pv in1 sw1 fb_b1 ldo1 en 725mv v in ldo1 fb_l1 buck2 v ref en ok default = 725mv range = 800mv to 412.5mv pv in2 sw2 fb_b2 dac buck3 v ref en ok default = 725mv range = 800mv to 412.5mv pv in3 sw3 fb_b3 dac buck4 ldo2 v ref en ok default = 725mv range = 800mv to 412.5mv precision enable threshold and sequence delay pv in4 sw4 v in_l2 ldo2 fb_b4 v ref 725mv en ok fb_l2 dac gnd (exposed pad) 36761 bd ldo3 v in_l3 ldo3 v ref en ok ldo4 v in_l4 ldo4 v ref en ok en_b1 5 5 5 pushbutton on/off control on wake en_b2 en_b3 i 2 c command registers dv dd dynamic voltage scaling control fault detection under voltage over temperature sda vttr vddqin vddqin/2 scl vstb en_b4 en_l2 en_l3 pwr_on rsto irq pgood vsel va 4x5 7 7 7 vb 4x5 ltc 3676/ ltc 3676-1 3676fd
15 for more information www.linear.com/ltc3676 o pera t ion introduction the ltc3676 is a complete power management solution for portable microprocessors and peripheral devices. it generates a total of eight voltage rails for supplying power to the processor core, ddr memory, i/o, always-on real- time clock and hdd functions. supplying the voltage rails are an always-on low quiescent current 25 ma ldo, two 2.5a step-down regulators, two 1.5 a step-down regula - tors, and three 300 ma low dropout regulators. supporting the multiple regulators is a highly configurable power-on sequencing capability, dynamic voltage scaling dac output voltage control, a pushbutton interface controller, control via an i 2 c interface, and extensive status and interrupt outputs. the ltc3676-1 supports ddr memory applications by replacing the ltc3676 ldo4 feedback and enable pins with vddqin and vttr pins. the ddr v dd supply is connected to the ltc3676-1 vddqin pin. a buffered ddr termination voltage equal to one half the voltage on vd - dqin is output on vtt r . the vttr voltage is connected internally on the ltc3676-1 to the reference side of the buck1 error amplifier. when buck1 is configured with a gain of one, its output can be used as at ddr termination supply. table ?1 shows the functional differences between the ltc3676 and ltc3676-1. table 1. functional differences ltc3676 vs ltc3676-1 ltc3676 ltc3676-1 buck1 default frequency 2.25mhz 1.125mhz buck1 default mode pulse-skipping forced continuous buck1 output external resistor divider. slewing dac reference external unity gain. vttr reference ldo4 enable en_l4 pin or i 2 c i 2 c ldo4 output external resistor divider. 725mv reference i 2 c select 1 of 4 fixed outputs fb_l4 pin external resistor divider en_l4 pin enable ldo4. vddqin pin connect to ddr memory supply vttr pin buffered output equals one-half vddqin i 2 c device address write = 0x78 read = 0x79 write = 0x7a read = 0x7b always-on 25ma low dropout regulator the ltc3676 includes a low quiescent current low dropout regulator that remains powered whenever a valid supply is present on v in . the always-on ldo1 remains active until v in drops below 2.0v ( typical). this is below the 2.5v undervoltage threshold in effect for the rest of the ltc3676 circuits. the always-on ldo is used to provide power to a standby microcontroller, real - time clock, or other keep - alive circuits. the ldo is guaranteed to support a 25 ma load. a 1 f low impedance ceramic bypass capacitor from ldo1 to gnd is required for compensation. a power good monitor pulls rsto low whenever ldo1 is 8% below its regulation target. ldo1 has current limit circuitry to protect from short circuit and overloading. the output voltage of ldo1 is set with a resistor divider connected from ldo1 output pin to the feedback pin fb_l1, as shown in figure 2. the output voltage is calculated using the following formula: v ldo1 = 725 ? 1 + r1 r2 ? ? ? ? ? ? mv ( ) 300ma low dropout regulators three ldo regulators on the ltc3676 will each deliver up to 300 ma output. each ldo regulator has separate input supply to help manage power loss in the ldo output devices. the ldo regulators are enabled by pin input or i 2 c command register. when disabled, the regulator outputs are pulled to ground through a 625 resistor. a low esr 1f ceramic capacitor should be tied from the ldo output to ground. the 300 ma ldo regulators have current limit control circuits. the ldo input voltages, v in_l2 , v in_l3 , and v in_l4 must be at potential of v in or less. the ldo regulator i 2 c command register controls are shown in table 2 and table 3. error amp buck1 pvinb1 sw1 fb_b1 c fb r1 c out 3676 f01 ddr ref vddqin/2 vddqin/2 vddqin vttr pwm figure 1. v tt buck regulator and vttr reference block diagram ltc 3676/ ltc 3676-1 3676fd
16 for more information www.linear.com/ltc3676 figure 2. ldo1, ldo2 and ldo4 application circuit o pera t ion ltc3676 resistor programmable ldo2 and ldo4 ldo2 and ldo4 output voltages are programmed by resis - tor dividers tied from the ldo output pin to the feedback pin as shown in figure 2. the output voltage is calculated using the following formula: v ldo = 725 ? 1 + r1 r2 ? ? ? ? ? ? mv ( ) output is 1.2 v with selectable outputs of 2.5v, 2.8 v, and 3.0v. ldo4 is enabled only through the command register bit ldob[2]. ldo4 command register controls table 3. ldo4 control command register settings command register[bit] value setting ldob[0] 0* 1 do not keep alive ldo4 in standby keep alive ldo4 in standby ldob[1] 0* 1 enable ldo4 at any output v oltage enable ldo4 only if output voltage is <300mv ldob[2] (ltc3676) 0* 1 ldo4 disabled if en_l4 is low ldo4 enabled ldob[2] (ltc3676-1) 0* 1 ldo4 disabled ldo4 enabled ldob[4:3] (ltc3676-1) 00* ldo4 output = 1.2v ldob[4:3] (ltc3676-1) 01 ldo4 output = 2.5v ldob[4:3] (ltc3676-1) 10 ldo4 output = 2.8v ldob[4:3] (ltc3676-1) 11 ldo4 output = 3v *denotes default power-on value. step-down switching regulators the ltc3676 contains four buck regulators. tw o of the buck regulators are capable of delivering up to 2.5 a load current and the other two can deliver up to 1.5 a each. the regulators have forward and reverse current limiting, soft- start, and switch slew rate control for lower radiated emi. the ltc3676 buck regulators are capable of 100% duty cycle, or dropout, regulation. when in dropout the regulator output voltage is equal to pv in minus the load current times r ds(on) of the converters pmos device and inductor dcr. each buck regulator is enabled using its enable pin or i 2 c command register control. operating modes, start-up op- tion, reference voltage, and switch slew rate are controlled using the i 2 c port. the buck converter i 2 c command register controls are shown in table 4, table 5, table 6, and table 7. + ? v in ldo fb r1 r2 3676 f02 1f 0.725v fixed output ldo3 regulator ldo3 has a fixed voltage output of 1.8v. table 2. ldo2 and ldo3 control command register settings command register[bit] value setting ldoa[0] 0* 1 do not keep alive ldo2 in standby keep alive ldo2 in standby ldoa[1] 0* 1 enable ldo2 at any output v oltage enable ldo2 only if output voltage is <300mv ldoa[2] 0* 1 ldo2 disabled if en_l2 is low ldo2 enable ldoa[3] 0* 1 do not keep alive ldo3 in standby keep alive ldo3 in standby ldoa[4] 0* 1 enable ldo3 at any output v oltage enable ldo3 0nly if output voltage is <300mv ldoa[5] 0* 1 ldo3 disabled if en_l3 is low ldo3 enabled *denotes default power-on value. ldo4 operation ltc3676-1 ldo4 on the ltc3676-1 has neither enable nor feedback pins. there are four ldo4 output voltages selectable by command register bits ldob[4:3]. the power-on default ltc 3676/ ltc 3676-1 3676fd
17 for more information www.linear.com/ltc3676 o pera t ion operating modes the buck regulators can operate in either pulse-skipping, burst mode operation, or forced continuous mode. in pulse-skipping setting the regulator will skip pulses at light loads but will operate at constant frequency. in burst mode setting the regulator operates in burst mode opera - tion at light loads and in constant frequency pw m mode at higher load. in forced continuous setting the inductor current is allowed to be less than zero over the full range of duty cycles. in forced continuous operation the buck regulator has the ability to sink output current. because the regulator is switching every cycle regardless of output load, forced continuous mode results in the least output voltage ripple at light load. output voltage programming each of the step- down converters uses a dynamically slew - ing dac for its reference. the output voltage of the dac reference is selectable using a 5- bit i 2 c command register. the output voltage is set by using a resistor divider con- nected from the step-down switching regulator output to its feedback pin as shown in figure 3. the output voltage is calculated using the following formula: v out = 1 + r1 r2 ? ? ? ? ? ? ? dvbx ? 12.5 + 412.5 ( ) mv ( ) dvbx is the decimal value of the 5- bit binary number in the i 2 c command registers. the default dac input code is 11001 (25 in decimal) which corresponds to a reference voltage of 725 mv. typical values for r1 are in the range of 40 k to 1 m. capacitor c fb cancels the pole created by the feedback resistors and the input capacitance on the fb pin and helps to improve load step transient response. a value of 10pf is recommended. inductor selection the choice of step-down switching regulator inductor influences the efficiency and output voltage ripple of the converter. a larger inductor improves efficiency since the peak current is closer to the average output current. larger inductors generally have higher series resistance that counters the efficiency advantage of reduced peak current. inductor ripple current is a function of switching frequency, inductance, v in , and v out as shown in this equation: i l = 1 f ? l ? v out ? 1? v out v in ? ? ? ? ? ? a good starting design point is to use an inductor that gives ripple equal to 30% output current. select an induc- tor with a dc current rating at least 1.5 times larger than the maximum load current to ensure the inductor does not saturate. input and output capacitor selection low esr ceramic capacitors should be used at both the output and input supply of the switching regulators. only x5r or x7r ceramic capacitors should be used since they have better temperature and voltage stability than other ceramic types. operating frequency the switching frequency of each of the ltc3676 switching regulators may be set using the i 2 c command registers. the default switching frequency is 2.25mhz and the select - able frequency is 1.125 mhz. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses at the expense of a larger inductor. the lowest duty cycle of the step-down converter is de - termined by minimum on-time. minimum on-time is the shortest time duration that the converter can turn its top pmos on and off again. the time is the sum of gate charge figure 3. step-down switching regulator application circuit default 725mv dac 5 sw fb mode en c fb r1 c out r2 3676 f03 pv in pwm control 2 ltc 3676/ ltc 3676-1 3676fd
18 for more information www.linear.com/ltc3676 figure 4. phase settings full- and half-speed buck clock o pera t ion time plus internal delays of the peak current sense and pwm control. if the converters duty cycle will be 20% or less at 2.25 mhz it is recommended to use the 1.125mhz setting to avoid minimum duty cycle. if the duty cycle falls below the minimum on-time of the converter, the output voltage ripple will increase as the converter skips cycles. the default setting for the ltc3676-1 buck1 switching frequency is 1.125 mhz to ensure minimum on time ef - fects are avoided at ddr termination reference voltages. phase selection to reduce the cycle by cycle peak current drawn by the switching regulators, the clock phase at which each of the ltc3676 bucks pmos switch turns on can be set using i 2 c command register settings. table 4. buck1 control command register command register[bit] value setting buck1[0] 0* 1 switch slew rate normal switch slew rate fast buck1[1] 0* 1 do not keep enabled in device standby keep enabled in device standby buck1[2] (ltc3676) 0* 1 switching frequency 2.25mhz switching frequency 1.125mhz buck1[2] (ltc3676-1) 0* 1 switching frequency 1.125mhz switching frequency 2.25mhz buck1[3] 0* 1 clock phase 1 clock phase 2 buck1[4] 0* 1 enable at any output v oltage enable only if output voltage is <300mv buck1[6:5] 00* 01 10 pulse -skipping mode burst mode operation for ced continuous mode buck1[7] 0* 1 buck1 disabled if en_b1 pin is low buck1 enabled *denotes default power on-value. table 5. buck2 control command register command register[bit] value setting buck2[0] 0* 1 switch slew rate normal switch slew rate fast buck2[1] 0* 1 do not keep enabled in device standby keep enabled in device standby buck2[2] 0* 1 switching frequency 2.25mhz switching frequency 1.125mhz buck2[3] 0* 1 clock phase 1 clock phase 2 buck2[4] 0* 1 enable at any output v oltage enable only if output voltage is <300mv buck2[6:5] 00* 01 10 pulse -skipping mode burst mode operation for ced continuous mode buck2[7] 0* 1 buck2 disabled if en_b2 pin is low buck2 enabled *denotes default power-on value. 2.25mhz 1 2 1 1.125mhz 3676 f04 1 2 switch slew rate control to help reduce emi the switch rise time of each buck regula - tor is slew limited by default. a faster setting is selectable using the i 2 c buck command registers. the faster setting will improve efficiency if limited edge rate is not required. soft-start to reduce inrush current at start-up each buck regulator soft starts when enabled. when enabled the internal ref - erence voltage is ramped from ground to the level of the slewing dac output at a rate of 0.8 v/ms. during soft-start the converter is forced to pulse-skipping mode regardless of command register mode settings. ltc 3676/ ltc 3676-1 3676fd
19 for more information www.linear.com/ltc3676 o pera t ion table 6. buck3 control command register command register[bit] value setting buck3[0] 0* 1 switch slew rate normal switch slew rate fast buck3[1] 0* 1 do not keep enabled in device standby keep enabled in device standby buck3[2] 0* 1 switching frequency 2.25mhz switching frequency 1.125mhz buck3[3] 0* 1 clock phase 1 clock phase 2 buck3[4] 0* 1 enable at any output v oltage enable only if output voltage is <300mv buck3[6:5] 00* 01 10 pulse -skipping mode burst mode operation for ced continuous mode buck3[7] 0* 1 buck3 disabled if en_b3 pin is low buck3 enabled *denotes default power-on value. table 7. buck4 control command register command register[bit] value setting buck4[0] 0* 1 switch slew rate normal switch slew rate fast buck4[1] 0* 1 do not keep enabled in device standby keep enabled in device standby buck4[2] 0* 1 switching frequency 2.25mhz switching frequency 1.125mhz buck4[3] 0* 1 clock phase 1 clock phase 2 buck4[4] 0* 1 enable at any output v oltage enable only if output voltage is <300mv buck4[6:5] 00* 01 10 pulse -skipping mode burst mode operation for ced continuous mode buck4[7] 0* 1 buck4 disabled if en_b4 pin is low buck4 enabled *denotes default power-on value. slewing dac reference operation each ltc3676 step-down switching regulators error am- plifier reference voltage is supplied by a 5- bit dac with an output voltage range of 412.5 mv to 800 mv in 12.5mv steps. one of two 5- bit codes stored in i 2 c command registers is selected for input to the dac. when a change in code is detected by the dac control circuits, the output of the dac is slewed at 3.5mv/s to the new value. dynamic voltage scaling table 8 shows the command registers used to control dynamic voltage scaling ( dvs) of the step-down switching regulators input reference dac. the command register bits dvb1a[4:0] and dvb1b[4:0] store two 5- bit inputs to the dac reference for buck1. the bit stored in com - mand register dvb1a[5] selects either the 5 bits stored in dvb1a[4:0] or dvb1b[4:0] dac as input to the dac reference. buck2, buck3, and buck4 operate the same way using their assigned a and b command registers shown in table 8. when the dac detects a change in its input code it automatically slews to the new value at a rate of 3.5 mv/s. a dvs can be initiated using the i 2 c select bit or using the vstb pin. the ltc3676 vstb pin high selects the 5 bits stored in all four dvbx b registers. this facilitates a simultaneous dac slew between the values in the a registers and the values in the b registers. the vstb pin is logically ored with the i 2 c command register bit. if the i 2 c select bit is already set high, the b registers are already selected and vstb will have no effect. if no change in output is desired using the vstb pin, set the value in the a register equal to the value in the b. command register bits dvb1b[5], dvb2b[5], dvb3b[5], and dvb4b[5] control whether the pgood status pin is pulled low while the dac output is slewing. the default command register setting is to pull pgood pin low dur - ing dac slew. during the dvs, pgood will be held low for just the duration of the dvs and the pgst at register is not affected. figure 5. dynamic voltage scaling v out 200mv/div pgood 5v/div vstb 5v/div 100s/div 3676 f05 ltc 3676/ ltc 3676-1 3676fd
20 for more information www.linear.com/ltc3676 o pera t ion table 8. buck1, buck2, buck3, and buck4 slewing dac control command registers command register[bit] value setting dvb1a[4:0] bbbbb buck1 reference dac input a dvb1a[5] 0* 1 select dvb1a[4:0] select dvb1b[4:0] dvb1b[4:0] bbbbb buck1 reference dac input b dvb1b[5] 0* 1 pull pgood low slewing buck1 do not pull pgood slewing buck1 dvb2a[4:0] bbbbb buck2 reference dac input a dvb2a[5] 0* 1 select dvb2a[4:0] select dvb2b[4:0] dvb2b[4:0] bbbbb buck2 reference dac input b dvb2b[5] 0* 1 pull pgood low slewing buck2 do not pull pgood slewing buck2 dvb3a[4:0] bbbbb buck3 reference dac input a dvb3a[5] 0* 1 select dvb3a[4:0] select dvb3b[4:0] dvb3b[4:0] bbbbb buck3 reference dac input b dvb3b[5] 0* 1 pull pgood low slewing buck3 do not pull pgood slewing buck3 dvb4a[4:0] bbbbb buck4 reference dac input a dvb4a[5] 0* 1 select dvb4a[4:0] select dvb4b[4:0] dvb4b[4:0] bbbbb buck4 reference dac input b dvb4b[5] 0* 1 pull pgood low slewing buck4 do not pull pgood slewing buck4 *denotes default power-on value. pushbutton operation operating mode state diagram figure 6 shows the state diagram of the ltc3676 enable and sequence controller. first application of power to v in pin brings the controller to the power-on reset/hard reset ( por/hrst) state. in this state the i 2 c command registers have been set to their default values, only ldo1 is operating, and the device is waiting for pushbutton or pwr_on inputs. regulator enable pins and command register enable bits are ignored in por/hrst state. in the por/hrst state v in draws typically 12a. power up using pushbutton when the on pin is held low for 400 ms the wake pin is pulled high, enable pins are recognized, and the five second pwr_on timer is started. if in the on state and pwr_on is low or a fault is detected, then wake is brought low and after a 1 second power-down time, the standby state is entered. in standby, the enable bits in the command registers are cleared and enable pins are ignored. table ?9 shows the control of command registers, enables, and wake at each state. the 5 second power-on state is intended for the system to detect that power rails are correct and either drive pwr_ on pin high or set command register bit cntrl[7] high to keep the rails active. if there were a system level problem figure 6. ltc3676 operating mode state diagram enable allowed and wake high enable inhibited and wake low por/hrst v in high on 400ms or pwr_on on 10 sec or i 2 c hrst on 400ms or pwr_on pwr_on or fault on 10 sec or i 2 c hrst on 10 sec or i 2 c hrst 1 sec off timer hrst 3676 f06 1 sec off timer standby 5 sec pwr_on timer on standby ltc 3676/ ltc 3676-1 3676fd
21 for more information www.linear.com/ltc3676 o pera t ion keeping the processor from driving pwr_on, then the ltc3676 will pull wake low, shut off all regulators, and enter the standby state. the standby state is also a low power, 12a (typical) state. table 9. register, enable, wake control during operating mode state control state registers enables wake por/hrst default r/w inhibited low 5 sec pwr_on timer r/w allowed high on r/w allowed high 1 sec off timer hrst set to por defaults sequence down low 1 sec off timer standby i 2 c enable and sw mode bits cleared sequence down low standby r/w inhibited low power down using pushbutton when in the on state, the system controller is responsible for deciding what action to take when a pushbutton event occurs. by monitoring the irq status pin and irqstat[0] status register bit, the controller can detect a pushbutton request. if a power-down into standby state is desired then the controller should drive pwr_on low and set command register bit cntrl[7] low. button status indication when a pushbutton pulls on low for 50 ms in the on state, irq is pulled low and the pb status bit in the irqstat[0] status register is set. irq and the irqstat status bit are active while on is low or for a minimum of 50ms. power up and down with pwr_on the pwr_on pin is an alternative way to power up the ltc3676 instead of using the on pin. when pwr_on is driven high or command register cntrl[7] is set high, wake is pulled high and the ltc3676 passes through the 5 second pwr_on timer to the on state. figure 9 shows pwr_on and wake timing. wake stays high for a minimum of 5 seconds. figure 8. power-down using pushbutton 50ms irqstat[0] wake <10 sec on (pb) irq pwr_on (pin or i 2 c) 3676 f08 c/p control 3ms figure 7. power up using pushbutton 400ms on (pb) wake pwr_on (pin or i 2 c) <5 sec 3676 f07 c/p control figure 9. power up and down with pwr_on pwr_on (pin or i 2 c) wake 3676 f09 c/p control 5 sec 3ms 3ms power on sequencing enable pin operation the ltc3676 enable pins facilitate pin-strapping output rails to enable pins to up- sequence the ltc3676 regulators in any order. figure 10 shows an example of pin-strapped sequence connections. the enable pins normally have a 0.8v (typical) input voltage threshold. if any enable is driven high, the remaining enable input thresholds switches to an accurate 400 mv threshold. to ensure separation of the sequenced rails, there is a built- in 450 s delay from the enable pin threshold crossing to the internal enable of the regulator. figure 11 shows the start-up timing of the example shown in figure 10. ltc 3676/ ltc 3676-1 3676fd
22 for more information www.linear.com/ltc3676 figure 11. pin-strapped power-on sequence o pera t ion software control mode once a power-up sequence is completed, each regulator may be enabled and disabled individually by the system as needed for power management requirements by using the command register bit cntrl[5]. when cntrl[5] is set high the regulators ignore the state of their enable pins and respond only to i 2 c command register bit settings. the software control mode bit is reset in the one second standby and hard reset timer states so a pin strapped sequence begins at the next ltc3676 power on. keep alive operation each regulator has a dedicated command register keep alive bit that, when set, forces a regulator to be enabled regardless of the enable pins, command register enable wake v b1 v b2 v b3 v b4 v l2 v l3 v l4 0.4v 0.4v 450s 1.2v 1.8v 2.5v 1.2v 1.2v 1.8v 2.8v 3676 f11 450s 450s bits, or the operating state of the ltc3676. a hard reset or fault shutdown resets the keep alive bits. power off sequencing sequence down command registers sqd1 and sqd2 are used to set the time, relative to wake falling, that a regulator is disabled either by lowering pwr_on, or a fault induced shutdown. table 10 shows register settings for sqd1 and sqd2. table 10.sequence down control command register settings command register[bit] value setting sqd1[1:0] 00* 01 10 11 disable buck1 at falling w ake disable buck1 at falling wake + 100ms disable buck1 at falling wake + 200ms disable buck1 at falling wake + 300ms sqd1[3:2] 00* 01 10 11 disable buck2 at falling w ake disable buck2 at falling wake + 100ms disable buck2 at falling wake + 200ms disable buck2 at falling wake + 300ms sqd1[5:4] 00* 01 10 11 disable buck3 at falling w ake disable buck3 at falling wake + 100ms disable buck3 at falling wake + 200ms disable buck3 at falling wake + 300ms sqd1[7:6] 00* 01 10 11 disable buck4 at falling w ake disable buck4 at falling wake + 100ms disable buck4 at falling wake + 200ms disable buck4 at falling wake + 300ms sqd2[1:0] 00* 01 10 11 disable ldo2 at falling w ake disable ldo2 at falling wake + 100ms disable ldo2 at falling wake + 200ms disable ldo2 at falling wake + 300ms sqd2[3:2] 00* 01 10 11 disable ldo3 at falling w ake disable ldo3 at falling wake + 100ms disable ldo3 at falling wake + 200ms disable ldo3 at falling wake + 300ms sqd2[5:4] 00* 01 10 11 disable ldo4 at falling w ake disable ldo4 at falling wake + 100ms disable ldo4 at falling wake + 200ms disable ldo3 at falling wake + 300ms *denotes default power-on value. figure 12 shows an example of a shutdown sequence. in this example, the bits in command registers sqd1 and sqd2 are set so that ldo2, ldo3, and ldo4 shut off at the same time as wake. buck2 and buck4 shut off 100 ms after wake. buck3 shuts off 200 ms after wake and buck1 shuts off 300ms after wake. figure 10. pin-strapped power-on sequence application ltc3676 v in pwr_on 3676 f10 v b1 = 1.2v v b2 = 1.8v v b3 = 2.5v v b4 = 1.2v v l2 = 1.2v v l3 = 1.8v v l4 = 2.8v wake sw1 sw2 sw3 sw4 ldo2 ldo3 ldo4 en_b1 en_b2 en_b3 en_b4 en_l2 en_l3 en_l4 on pwr_on ltc 3676/ ltc 3676-1 3676fd
23 for more information www.linear.com/ltc3676 o pera t ion figure 13. output low voltage pgood and irq timing figure 12. power-down sequence 300ms 1.2v wake v b1 v b2 v b3 v b4 v l2 v l3 v l4 1.8v 2.5v 1.2v 1.2v 1.8v 2.8v 3676 f12 200ms 100ms fault detection and reporting the ltc3676 has fault detection circuits that monitor for v in undervoltage, die overtemperature, and regulator output undervoltage. status of the fault detect circuits is indicated by the irq and pgood pins and the irqstat and pgstat status registers. v in undervoltage the undervoltage ( uv) circuit monitors the input supply voltage, v in , and when the voltage falls below 2.45 v cre- ates a fault condition that forces the ltc3676 into the standby state. the ltc3676 also provides a ( uv) warning that is triggered at user programmable v in voltages as shown in table 11. table 11. undervoltage warning threshold command register settings command register[bit] value falling v in threshold cntrl[4:2] 000* 001 010 011 100 101 110 111 2.7 v 2.8v 2.9v 3.0v 3.1v 3.2v 3.3v 3.4v * denotes default power-on value. 450s enx v outx pgood irq 50s 50s 1ms 1ms 20ms 3676 f13 over temperature to prevent thermal damage the ltc3676 incorporates an overtemperature ( ot) circuit. when the die temperature reaches 155 c the ot circuits create a fault condition that forces the ltc3676 into standby. when the ot cir - cuit detects the temperature falls below 140 c the fault condition is cleared. the ltc3676 also has an ot warning circuit that indicates the die temperature is approaching the ot fault threshold. the ot warning threshold is user programmable as shown in table 12. table 12. overtemperature warning threshold command register settings command register[bit] value ot warning threshold cntrl[1:0] 00* 01 10 11 10 c below ot fault 20c below ot fault 30c below ot fault 40c below ot fault *denotes default power-on value. pgood status pin the pgood open-drain status pin is pulled low when all regulators are disabled. pgood is released when all enabled regulator outputs are above 93% of programmed value. when any enabled regulator output falls below 92% of its programmed value for longer than 50 s the pgood pin is pulled low. the 50 s transient filter on pgood prevents pgood glitches due to transients. if the error condition persists for longer than 20 ms, the irq pin is pulled low and status register irqstat bit 2 is set to indicate a persistent pgood fault. the pgood pin is held low for the duration of the low output condition plus 1 ms. figure 13 shows the timing of pgood during enable and fault events. ltc 3676/ ltc 3676-1 3676fd
24 for more information www.linear.com/ltc3676 o pera t ion pgstat and mskpg registers the power good status of each regulator is accessible through the ltc3676 i 2 c interface by reading the contents of the pgstat status register. table 13 shows the pgstat register contents. the data in the pgstatl register is held for the length of the low voltage condition plus 1 ms. the data in the pgstatrt register is held only for the duration of the low voltage condition. table 13. power good status register status register[bit] value regulator output low status pgstat[0] 0 1 buck 1 output low buck1 output ok pgsta t[1] 0 1 buck2 output low buck2 output ok pgsta t[2] 0 1 buck3 output low buck3 output ok pgsta t[3] 0 1 buck4 output low buck4 output ok pgsta t[4] 0 1 ldo1 output low ldo1 output ok pgsta t[5] 0 1 ldo2 output low ldo2 output ok pgsta t[6] 0 1 ldo3 output low ldo3 output ok pgsta t[7] 0 1 ldo4 output low ldo4 output ok each regulator has a corresponding bit in the mskpg status register as shown in table 14. when set, a bit blocks the pgood pin from being pulled low in the event of a low output voltage fault from its matching regulator. setting a bit in the mskpg command register does not mask the status in the pgstat status register. table 14. power good status masking command register command register[bit] value mskpg [0] 0 1* mask buck1 pgood status pass buck1 pgood status mskpg [1] 0 1* mask buck2 pgood status pass buck2 pgood status mskpg [2] 0 1* mask buck3 pgood status pass buck3 pgood status mskpg [3] 0 1* mask buck4 pgood status pass buck4 pgood status mskpg [5] 0 1* mask ldo2 pgood status pass ldo2 pgood status mskpg [6] 0 1* mask ldo3 pgood status pass ldo3 pgood status mskpg [7] 0 1* mask ldo4 pgood status pass ldo4 pgood status *denotes default power-on value. irq status pin the irq pin is pulled and latched low when undervoltage, overtemperature or persistent pgood events occur. the irq pin is cleared by addressing the clirq command register or by holding on low for 50ms. table 15. interrupt request status register status register[bit] value irqstat register bit meaning irqstat [0] 0 1 pushbutton status active (real time) irqst a t [1] 0 1 hard reset occurred irqsta t [2] 0 1 pgood timeout occurred irqsta t [3] 0 1 undervoltage warning irqsta t [4] 0 1 undervoltage standby occurred irqsta t [5] 0 1 overtemperature warning irqsta t [6] 0 1 overtemperature standby occurred ltc 3676/ ltc 3676-1 3676fd
25 for more information www.linear.com/ltc3676 o pera t ion irqstat and mskirq registers the bits in the mskirq command register are set to mask warning, fault, and pushbutton status reporting to the irq pin. when set to mask, the irq pin is not pulled low as a result of a fault or warning. even though the irq pin is not pulled low the masked bit is set in the irqstat register. when undervoltage, overtemperature faults, and hard reset signals are masked, the irq pin is not pulled low but ltc3676 state controller is pushed into the standby or por/hrst state. accessing the clirq status register clears the latched bits in the irqstat status register and releases the irq pin. table 16. interrupt request mask command register command register[bit] value mskirq [0] 0* 1 pass pushbutton status mask pushbutton status mskirq [2] 0* 1 pass pgood t imeout mask pgood timeout mskirq [3] 0* 1 pass under voltage warning mask undervoltage warning mskirq [4] 0* 1 pass under voltage shutdown mask undervoltage shutdown mskirq [5] 0* 1 pass overtemperature w arning mask overtemperature warning mskirq [6] 0* 1 pass overtemperature shutdown mask overtemperature shutdown *denotes default power-on value. irq and irqstat are not cleared by hard reset or fault shutdown. if v in remains applied while the ltc3676 is in standby or por/hrst then irqstat may be read on the subsequent power up to determine if a fault or hard reset occurred. rsto status pin the ltc3676 rsto status pin is pulled low when always- on ldo1 is 8% below its programmed value or when the ltc3676 is in the one second hrst timer state. hard reset a hard reset can be initiated by holding the on pin low or writing to the hrst command register. bit six of the cntrl command register determines how long on must remain low to initiate the hard reset. a hard reset sets all i 2 c command register bits to their default power-on state. table 17 shows the command register control of hard reset function. table 17. hard reset time control command register command register[bit] value setting cntrl[6] 0* 1 10 seconds 5 seconds *denotes default power-on value. a hard reset command will push the ltc3676 state con- troller through the 1 second hrst timer state and into the por/hrst state. fault shutdown an undervoltage or overtemperature fault will push the ltc3676 state controller through the 1 second standby timer state and into standby state. if a down sequence is selected in the command registers, it will be executed during the 1 second power down interval. ltc3676-1 operation the ltc3676-1 option supports ddr memory operation by generating a ddr termination reference and supply rail equal to one-half the voltage applied to vddqin pin 8. an internal resistive divider creates a reference voltage of one-half the voltage on vddqin. this reference is used by the v tt reference buffer to output one-half of vddqin on vttr pin 9. the vttr voltage is used as the reference for 1.5 a switching regulator 1 which is used as the ddr termination supply. the ltc3676-1 en_b1 pin and com - mand register bit buck1[7] enable both vttr output and switching regulator 1. figure 1 shows typical application connections for the ltc3676-1 ddr termination reference and termination supply. ldo4 has i 2 c command register selectable output volt- ages of 1.2 v (default), 2.5v, 2.8 v and 3 v and is enabled only using the i 2 c command register. table 18 shows the ldo4 command register controls for the ltc3676-1. ltc 3676/ ltc 3676-1 3676fd
26 for more information www.linear.com/ltc3676 o pera t ion table 18. ldo4 control command register setting (ltc3676-1) command register[bit] value setting ldob[0] 0* 1 do not keep alive ldo4 in standby keep alive ldo4 in standby ldob[1] 0* 1 enable ldo4 at any output v oltage enable ldo4 only if output voltage is <300mv ldob[2] 0* 1 ldo4 disabled ldo4 enable ldob[4:3] 00* 01 10 11 1.2 v 2.5v 2.8v 3.0v *denotes default power-on value. i 2 c operation the ltc3676 communicates with a bus master using the standard i 2 c 2- wire interface. the timing diagram in figure? 14 shows the relationship of the signals on the bus. the two bus lines, sda and scl must be high when the bus is not in use. external pull-up resistors or current sources, such as the ltc1694 smbus accelerator, are required on sda and scl. the ltc3676 is both a slave receiver and slave transmitter. the i 2 c control signals, sda and scl are scaled internally to the dv dd supply. dv dd must be connected to the same power supply as the bus pull-up resistors. the i 2 c port has an undervoltage lockout on the dv dd pin. when dv dd is below approximately 1 v, the i 2 c serial port is cleared and the command registers are set to default por values. the complete i 2 c command register table is shown in table 20. i 2 c bus speed the i 2 c port operates at speeds up to 400 khz. it has built in timing delays to ensure correct operation when addressed from an i 2 c compliant master device. it also contains input filters designed to suppress glitches should the bus become corrupted. i 2 c start and stop conditions a bus master signals the beginning of communications by transmitting a start condition. a start condition is generated by transitioning sda from high to low while scl is high. the master may transmit either the slave write or the slave read address. once data is written to the ltc3676, the master may transmit a stop condition which commands the ltc3676 to act upon its new command set. a stop condition is sent by the master by transition - ing sda from low to high while scl is high. the bus is then free for communication with another i 2 c device. i 2 c byte format each byte sent to or received from the ltc3676 must be 8 bits long followed by an extra clock cycle for the acknowledge bit. the data should be sent to the ltc3676 most significant bit (msb) first. i 2 c acknowledge the acknowledge signal is used for handshaking between the master and the slave. when the ltc3676 is written to, it acknowledges its write address and subsequent data bytes. when it is read from, the ltc3676 acknowledges its read address only. the bus master should acknowledge data returned from the ltc3676. an acknowledge generated by the ltc3676 lets the master know that the latest byte of information was received. the master generates the acknowledge related clock and releases the sda line during the acknowledge clock cycle. the ltc3676 pulls down the sda line during the write acknowledge clock pulse so that it is a stable low during the high period of this clock pulse. at the end of a byte of data transferred from the ltc3676 during a read operation, the ltc3676 releases the sda line to allow the master to acknowledge receipt of the data. failure of the master to acknowledge data from the ltc3676 has no effect on the operation of the i 2 c port. ltc 3676/ ltc 3676-1 3676fd
27 for more information www.linear.com/ltc3676 o pera t ion i 2 c slave address the ltc3676 responds to factory programmed read and write addresses. the least significant bit of the address byte is 0 when writing data and 1 when reading data. table 19 shows read and write addresses for the ltc3676 options. table 19. ltc3676 and ltc3676-1 i 2 c read and write addresses lt c part number r/ w address ltc3676 w 0111 1000, 0x78 ltc3676 r 0111 1001, 0x79 ltc3676-1 w 0111 1010, 0x7a ltc3676-1 r 0111 1011, 0x7b i 2 c write operation the ltc3676 has twenty-two command registers for control input. they are accessed by the i 2 c port via a sub-addressed writing system. a single write cycle of the ltc3676 consists of exactly three bytes except when a clear interrupt or hard reset command is written. the first byte is always the ltc3676 write address. the second byte represents the ltc3676 sub-address. the sub-address is a pointer which directs the subsequent data byte within the ltc3676. the third byte consists of the data to be written to the location pointed to by the sub-address. as shown in figure 15, the ltc3676 supports multiple sub-addressed write operations. data pairs sent following the chip write address are interpreted as sub-address and data. any number of sub-address and data pairs may be sent. the data in the command registers is not acted on by the ltc3676 until a stop signal is issued. the ltc3676 will keep interim writes to the registers when a repeat start condition occurs. a repeat start may be used to set up other devices on the i 2 c bus prior to send- ing a stop condition. the ltc3676 will act on the data written prior to the repeat start when a stop condition is detected. i 2 c read operation figure 16 shows the ltc3676 command register read sequence. the bus master reads a byte of data from a ltc3676 command or status register by first writing the ltc3676 write address followed by the sub-address to be read from. the ltc3676 acknowledges each of the two bytes. next, the bus master initiates a new start condition and sends the ltc3676 read address. follow - ing the acknowledge of the read address by the ltc3676, the ltc3676 pushes data onto the i 2 c bus for the 8 clock cycles. the bus master then acknowledges the data on its ninth clock. the last read sub-address that is written to the ltc3676 is stored. this allows repeated polling of a command or status register without the need to re- write its sub- address. additionally, the last register written may be immedi - ately read by issuing a start condition followed by read address and clocking out the data. figure 14. ltc3676 i 2 c serial port timing t su, dat t hd, sta t hd, dat sda scl t su, sta t hd, sta t su, sto 3676 f14 t buf t low t high start condition repeated start condition stop condition start condition t r t f t sp ltc 3676/ ltc 3676-1 3676fd
28 for more information www.linear.com/ltc3676 o pera t ion figure 15. ltc3676 i 2 c serial port multiple write pattern figure 16. ltc3676 i 2 c serial port read pattern 1 2 3 4 5 6 7 8 0 0 1 1 1 1 1 1 1 1 address 0 0 0 0 0 w 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 ack 3676 f15 ack ack ack ack start sda scl stop s7 s6 s5 s4 s3 sub address s2 s1 s0 d7 d6 d5 d4 d3 data d2 d1 d0 s7 s6 s5 s4 s3 sub address s2 s1 s0 d7 d6 d5 d4 d3 data d2 d1 d0 0 start sda scl 1 1 1 1 2 3 4 5 6 7 8 10 1 1 1 0 0 0 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 10011110 start 9 1 2 3 4 5 6 7 8 9 3676 f16 ack ack ack ack stop 1 address 0 0 w s7 s6 s5 s4 s3 sub address s2 s1 s0 0 1 1 1 1 address 0 0 r r7 r6 r5 r4 r3 data r2 r1 r0 ltc 3676/ ltc 3676-1 3676fd
29 for more information www.linear.com/ltc3676 o pera t ion reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x01 buck1 enable: 0 = disabled if en_b1 low 1 = enabled mode: 00 = pulse-skipping 01 = burst 10 = forced continuous start -up: 0 = enable at any output voltage 1 = enable only if output <300mv phase select: 0 = clock phase 1 1 = clock phase 2 clock rate: 0 = 2.25mhz 1 = 1.125mhz keep alive buck1: 0 = do not keep alive 1= keep alive in shutdown. switch dv/dt control: 0 = slow 1 = fast 0000 0000 0 x02 buck2 enable: 0 = disabled if en_b2 low 1 = enabled mode: 00 = pulse-skipping 01 = burst 10 = forced continuous start -up: 0 = enable at any output voltage 1 = enable only if output <300mv phase select: 0 = clock phase 1 1 = clock phase 2 clock rate: 0 = 2.25mhz 1 = 1.125mhz keep alive buck2: 0 = do not keep alive 1 = keep alive in shutdown switch dv/dt control: 0 = slow 1 = fast 0000 0000 0 x03 buck3 enable: 0 = disabled if en_b3 low 1 = enabled mode: 00 = pulse-skipping 01 = burst 10 = forced continuous start -up: 0 = enable at any output voltage 1 = enable only if output <300mv phase select: 0 = clock phase 1 1 = clock phase 2 clock rate: 0 = 2.25mhz 1 = 1.125mhz keep alive buck3: 0 = do not keep alive 1 = keep alive in shutdown switch dv/dt control: 0 = slow 1 = fast 0000 0000 0 x04 buck4 enable: 0 = disabled if en_b4 low 1 = enabled mode: 00 = pulse-skipping 01 = burst 10 = forced continuous start -up: 0 = enable at any output voltage 1 = enable only if output <300mv phase select: 0 = clock phase 1 1 = clock phase 2 clock rate: 0 = 2.25mhz 1 = 1.125mhz keep alive buck4: 0 = do not keep alive 1 = keep alive in shutdown switch dv/dt control: 0 = slow 1 = fast 0000 0000 0 x05 ldoa reserved reserved enable ldo3: 0 = disabled if en_l3 low 1 = enabled start-up ldo3: 0 = enable at any output voltage 1 = enable only if output <300mv keep alive ldo3: 0 = do not keep alive 1 = keep alive in shutdown. enable ldo2: 0 = disabled if en_l2 low 1 = enabled start-up ldo2: 0 = enable at any output voltage 1 = enable only if output <300mv keep alive ldo2: 0 = do not keep alive 1 = keep alive in shutdown xx00 0000 0x06 ldob reserved reserved reserved ltc3676-1 ldo4 output voltage: 00 = 1.2v 01 = 2.5v 10 = 2.8v 11 = 3.0v enable ldo4: 0 = disabled if en_l4 low 1 = enabled start-up ldo4: 0 = enable at any output voltage 1 = enable only if output <300mv keep alive ldo4: 0 = do not keep alive 1 = keep alive in shutdown xx00 0000 0x07 sqd1 sequence down buck4: 00 = with wake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms sequence down buck3: 00 = with w ake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms sequence down buck2: 00 = with w ake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms sequence down buck1: 00 = with w ake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms 0000 0000 table 20. ltc3676 command registers ltc 3676/ ltc 3676-1 3676fd
30 for more information www.linear.com/ltc3676 o pera t ion reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x08 sqd2 reserved reserved sequence down ld04: 00 = with wake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms sequence down ld03: 00 = with w ake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms sequence down ld02: 00 = with w ake 01 = wake + 100ms 10 = wake + 200ms 11 = wake + 300ms xx 00 0000 0x09 cntrl pwr_on: 0 = not pwr_on 1 = pwr_on "ored" with pwr_on pin pushbutton hard reset timer: 0 = 10 sec 1 = 5 sec software control mode: 0 = pin or register control 1 = inhibit pin control uv warning threshold: 000 = 2.7v 001 = 2.8v 010 = 2.9v 011 = 3.0v 100 = 3.1v 101 = 3.2v 110 = 3.3v 111 = 3.4v over temperature warning levels: 00 = 10 c below overtemperature 01 = 20 c below overtemperature 10 = 30 c below overtemperature 11 = 40 c below overtemperature 0000 0000 0x0a dvb1a reserved reserved buck1 reference select: 0 = dvb 1a[4-0] 1 = dvb1b[4-0] buck1 feedback reference input (va ): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 0x0b dvb1b reserved reserved pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing buck1 feedback reference input (vb): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 0x0c dvb2a reserved reserved buck2 reference select: 0 = dvb 2a[4-0] 1 = dvb2b[4-0] buck2 feedback reference input (va ): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx 01 1001 0x0d dvb2b reserved reserved pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing buck2 feedback reference input (vb): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 0x0e dvb3a reserved reserved buck3 reference select: 0 = dvb 3a[4-0] 1 = dvb3b[4-0] buck3 feedback reference input (va ): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 ltc 3676/ ltc 3676-1 3676fd
31 for more information www.linear.com/ltc3676 reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] default 0x0f dvb3b reserved reserved pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing buck3 feedback reference input (vb): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 0x10 dvb4a reserved reserved buck4 reference. select: 0 = dvb 4a[4-0] 1 = dvb4b[4-0] buck4 feedback reference input (va ): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 0x11 dvb4b reserved reserved pgood mask: 0 = pgood low when slewing 1 = pgood not forced low when slewing buck4 feedback reference input (vb): 00000 = 412.5mv 11001 = 725mv 11111 = 800mv 12.5mv step size xx01 1001 0x12 mskirq reserved mask over- temperature shutdown mask over- temperature warning mask undervoltage shutdown mask undervoltage warning mask pgood timeout reserved mask push button status x000 00x0 0x13 mskpg allow ldo 4 pgood fault allow ldo 3 pgood fault allow ldo 2 pgood fault reserved allow buck 4 pgood fault allow buck 3 pgood fault allow buck 2 pgood fault allow buck 1 pgood fault 1111 1111 0x14 user user bit 7 user bit 6 user bit 5 user bit 4 user bit 3 user bit 2 user bit 1 user bit 0 0000 0000 0x1e hrst hard reset command. no data. 0x1f clirq clear irq command. no data table 22. ltc3676 status registers reg name b[7] b[6] b[5] b[4] b[3] b[2] b[1] b[0] 0x15 irqstat reserved over- temperature shutdown over- temperature warning undervoltage shutdown undervoltage warning pgood timeout hard reset pushbutton status (real time) 0x16 pgstatl ldo4 pgood hold 1ms ldo3 pgood hold 1ms ldo2 pgood hold 1ms ldo1 pgood hold 1ms buck4 pgood hold 1ms buck3 pgood hold 1ms buck2 pgood hold 1ms buck1 pgood hold 1ms 0x17 pgstatrt ldo4 pgood ldo3 pgood ldo2 pgood ldo1 pgood buck4 pgood buck3 pgood buck2 pgood buck1 pgood o pera t ion ltc 3676/ ltc 3676-1 3676fd
32 for more information www.linear.com/ltc3676 applications information thermal considerations and board layout printed circuit board power dissipation in order to ensure optimal performance and the ability to deliver maximum output power to any regulator, it is critical that the exposed ground pad on the backside of the ltc3676 package be soldered to a ground plane on the board. the exposed pad is the only gnd connection for the ltc3676. correctly soldered to a 2500mm 2 ground plane on a double-sided 1 oz copper board, the ltc3676 has a thermal resistance( ? ja ) of approximately 34 c/w . failure to make good thermal contact between the exposed pad on the backside of the package and an adequately sized ground plane will result in thermal resistances far greater than 34c/w. to ensure the junction temperature of the ltc3676 die does not exceed the maximum rated limit and to prevent overtemperature faults, the power output of the ltc3676 must be managed by the application. the total power dissipation in the ltc3676 is approximated by summing the power dissipation in each of the switching regulators and the ldo regulators. the power dissipation in a switching regulator is estimated by: p d swx ( ) = v outx ? i outx ? 100-eff% 100 w ( ) where v outx is the programmed output voltage i outx is the load current and eff is the % efficiency that can be measured or looked up from the efficiency curves for the programmed output voltage. the power dissipated by an ldo regulator is estimated by: p d(ldox) = v in(ldox) ? v ldox ? i ldox (w) where v ldox is the programmed output voltage, v in(ldox) is the ldo supply voltage, and i ldox is the output load current. if one of the switching regulator outputs is used as an ldo supply voltage, remember to include the ldo supply current in the switching regulator load current for calculating power loss. an example using the equations above with the param - eters in table 23 shows an application that is at a junction temperature of 120 c at an ambient temperature of 55c. ldo2, ldo3, and ldo4 are powered by step-down buck2 and buck4. the total load on buck2 and buck4 is the sum of the application load and the ldo load. this example is with the ldo regulators at one third rated current and the switching regulators at three quarters rated current. table 23. ltc3676 power loss example v in v out application load (a) total load (a) eff (%) p d (mw) ldo1 3.8 1.2 0.01 0.010 C 26.00 ldo2 1.8 1.2 0.1 0.100 C 60.00 ldo3 3.3 1.8 0.1 0.100 C 150.00 ldo4 3.3 2.5 0.1 0.100 C 80.00 buck1 3.8 1.2 1.875 1.875 80 450.00 buck2 3.8 1.8 1.775 1.875 85 506.25 buck3 3.8 1.25 1.125 1.125 80 281.25 buck4 3.8 3.3 0.925 1.125 90 371.25 total power = 1925 internal junction temperature at 55c ambient 120c printed circuit board layout when laying out the printed circuit board, the following checklist should be followed to ensure proper operation of the ltc3676: 1. connect the exposed pad of the package (pin 41) di - rectly to a large ground plane to minimize thermal and electrical impedance. 2. the switching regulator input supply traces to their decoupling capacitors should be as short as possible. connect the gnd side of the capacitors directly to the ground plane of the board. the decoupling capacitors provide the ac current to the internal power mosfets and their drivers. it is important to minimize inductance from the capacitors to the ltc3676 pins. 3. minimize the switching power traces connecting sw1, sw2, sw3, and sw4 to the inductors to reduce radi - ated emi and parasitic coupling. keep sensitive nodes such as the feedback pins away from or shielded from the large voltage swings on the switching nodes. 4. minimize the length of the connection between the step- down switching regulator inductors and the output capacitors. connect the gnd side of the output capaci - tors directly to the thermal ground plane of the board. ltc 3676/ ltc 3676-1 3676fd
33 for more information www.linear.com/ltc3676 typical a pplica t ions ltc3676 pmic configured to support freescale i.mx6 processor 20 27 v in 3.3v to 5v v rtc 3v 25ma wake arm v ddhigh i/o 28 26 36 35 16 15 10pf 22f 22f 22f 22f 178k 47f 1h (1.37v) (1.37v) (3.3v) 22 1f 634k 200k 1f vddarm_in vddhigh_in vddsoc_in vdd_ddr_io vsnvs_in arm 0.9v to 1.5v at 2.5a freescale i.mx6 200k 68k 68k 4.7k 4.7k 68k 68k 40 10pf 178k 47f 1.5h 24 200k 31 10pf 715k 47f 1.5h 25 soc 0.9v to 1.5v at 1.5a ddr 1.5v at 2.5a 200k 11 10pf 1f 1f 215k 47f 1h 23 v ddhigh 2.97v 300ma i/o 3.3v 1.5a 200k sw3 v in ldo1 fb_l1 rsto rsto i/o wake en_b1 en_b2 en_b3 en_b4 en_l2 en_l3 en_l4 fb_b3 sw1 fb_b1 sw2 fb_b2 sw4 fb_b4 619k 200k ldo2 fb_l2 2 3 1f ldo3 4 1 1f ldo4 3v 300ma ldo3 1.8v 300ma 634k 200k 3676 ta02 41 ldo4 fb_l4 gnd ltc3676 gnd ddr 4 chips no term 6 8 v in_l2 1f 5 v in_l3 1f 7 v in_l4 pv in4 pv in3 pv in2 pv in1 33 37 34 18 17 30 10 9 38 irq irq 32 pgood pgood scl 39 scl 14 sca sda 13 vstb vstb 19 pwr_on pwr_on 21 on 29 dv dd 12 wake sequence: arm soc i/o ddr vddhigh ldo3 ltc 3676/ ltc 3676-1 3676fd
34 for more information www.linear.com/ltc3676 typical a pplica t ions ltc3676-1 pmic configured to support freescale i.mx6 processor with ddr v tt and vttr 20 27 v in 3v to 5.5v ldo1 3v 25ma wake v ddhigh arm 28 26 36 35 16 15 10pf 22f 22f 22f 22f 178k 47f 1h (1.37v) (1.37v) 22 1f 634k 200k 1f vddarm_in vddsoc_in vdd_ddr_io vsnvs_in vddhigh_in v ddhigh arm 0.9v to 1.5v at 2.5a freescale i.mx6 200k 68k 68k 4.7k 4.7k 68k 68k 31 10pf 10pf 178k 47f 1.5h 25 200k 215k 200k 11 47f 1h 23 soc 0.9v to 1.5v at 1.5a 40 10pf 215k 47f 1h 24 0.047f ddr 1.5v at 2.5a v tt 0.75v at 1.5a sw3 v in ldo1 fb_l1 rsto rsto i/o wake en_b1 en_b2 en_b3 en_b4 en_l2 en_l3 fb_b3 sw2 fb_b2 sw4 fb_b4 sw1 fb_b1 vddqin 8 vttr 9 1f ldo3 1.8v 300ma ldo3 4 1f v ddhigh 2.97v 300ma 619k 200k 3676 ta03 41 ldo2 fb_l2 gnd ltc3676-1 gnd ddr 8 chips with term 3 1 1f 2 v in_l2 1f 5 v in_l3 1f ldo4 3v 300ma ldo4 6 1f 7 v in_l4 pv in4 pv in3 pv in2 pv in1 33 37 34 18 17 30 10 38 irq irq 32 pgood pgood scl 39 scl 14 sca sda 13 vstb vstb 19 pwr_on pwr_on 21 on 29 dv dd 12 wake sequence: arm soc ddr vtt vddhigh ldo3 ltc 3676/ ltc 3676-1 3676fd
35 for more information www.linear.com/ltc3676 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) ltc 3676/ ltc 3676-1 3676fd
36 for more information www.linear.com/ltc3676 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. lxe48 (aa) lqfp 0612 0 ? 7 11 ? 13 0.45 ? 0.75 1.00 ref 11 ? 13 1 48 1.60 max 1.35 ? 1.45 0.05 ? 0.15 0.09 ? 0.20 0.50 bsc 0.17 ? 0.27 gauge plane 0.25 note: 1. dimensions are in millimeters 2. dimensions of package do not include mold flash. mold flash shall not exceed 0.25mm on any side, if present 3. pin-1 indentifier is a molded indentation, 0.50mm diameter 4. drawing is not to scale r0.08 ? 0.20 7.15 ? 7.25 5.50 ref 1 36 25 12 5.50 ref 7.15 ? 7.25 48 13 24 37 c0.30 package outline recommended solder pad layout apply solder mask to areas that are not soldered bottom of package?exposed pad (shaded area) side view section a ? a 0.50 bsc 0.20 ? 0.30 1.30 min 9.00 bsc a a 7.00 bsc 1 12 7.00 bsc 4.15 0.10 4.15 0.10 9.00 bsc 48 37 13 24 37 13 24 36 36 25 25 see note: 3 c0.30 ? 0.50 4.15 0.05 4.15 0.05 c0.30 lxe package 48-lead plastic exposed pad lqfp (7mm 7mm) (reference ltc dwg #05-08-1927 rev ?) exposed pad variation aa 12 ltc 3676/ ltc 3676-1 3676fd
37 for more information www.linear.com/ltc3676 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 12/13 modified the typical application circuit modified start-up sequence path changed conditions on v in burst mode quiescent current removed transient response comment from v out programming modified command registers table modified p d equation in pcb power dissipation section table 23 changed r and c values in typical applications 1 1 3 16 28-30 31 32, 33, 36 b 9/14 changed c values in application circuits corrected pin names in conditions in electrical characteristics table corrected units on current limit graph corrected units on ldo1 dropout and ldo1 load response graphs corrected operation introduction section modified ltc3676-1 operation section changed table reference in i 2 c operation section changed table number for command registers section clarified command registers table 1, 32, 33, 36 3 to 5 8 9 14 24 25 28 30 c 9/14 added lqfp package (lxe) 1 to 3, 11, 12, 36 d 05/15 modified thermal resistance of lxe package modified pin description of en_b1 modified figure 1 gnd clarified ltc3676-1 operation section amended package drawing 2 12 15 25 36 ltc 3676/ ltc 3676-1 3676fd
38 for more information www.linear.com/ltc3676 ? linear technology corporation 2013 lt 0515 rev d ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3676 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3101 1.8v to usb, multioutput dc/ dc converter with low loss usb power controller seamless transition between multiple input power sources, v in range: 1.8v to 5.5v, buck-boost converter v out range: 1.5v to 5.25v, 3.3v out at 800ma for v in 3v, dual 350ma buck regulators, v out : 0.6v to v in , 38a quiescent current in burst mode operation, 24-lead 4mm ? 4mm ? 0.75mm qfn package ltc3375 8-channel programmable, parallelable 1a buck dc/dcs 8-channel independent step-down dc/dcs. master slave configurable for up to 4a per output channel with a single inductor, die temperature monitor output, 48-lead 7mm ? 7mm qfn package ltc3589/ ltc3589-1/ ltc3589-2 8-output regulator with sequencing and i 2 c triple i 2 c adjustable high efficiency step-down dc/dc converters: 1.6a, 1a, 1a. high efficiency 1.2a buck-boost dc/dc converter. triple 250ma ldo regulators. pushbutton on/off control with system reset. flexible pin-strap sequencing operation. i 2 c and independent enable control pins, dvs and slew rate control, 40-lead 6mm ? 6mm ? 0.75mm qfn package ltc3586/ ltc3586-1 switching usb power manager pmic with li-ion/polymer charger complete multifunction pmic: switching power manager, 1a buck-boost + 2 bucks + boost + ldo, 4mm ? 6mm qfn-38 package, ltc3586-1 version has 4.1v v float . sequenced power for high performance processor and ddr memory using ltc3375 parallelable buck converters 174k 22f 22f 22f 22f sw1 sw2 vin_l3 ldo3 10pf 47f 47f 47f 47f 1f 100f 1f 4.7k 1f 0.01f 215k v in 5v 634k 21.5k 200k 200k pwr_on v in fb_b1 ldo1 fb_l1 vin_l2 power good from v in supply io18 1.8v 1.5a v rtc 3v 25ma 1f 576k 200k ldo2 fb_l2 2.8v 300ma io33 io18analog 1.8v 300ma 1.2v 300ma vttr 750mv 10ma v tt 0.75v 1.5a soc 1.35v 2.5a ltc3676-1 gnd pv in1 pv in2 pv in3 1.5h 2.2h 10pf 294k 200k fb_b2 1.5h sw3 10pf 174k 200k fb_b3 1h v ddhigh 3v 2.5a sw4 1f io33 10f 10pf 634k 200k fb_b4 ldo4 1f en_b1 en_b2 en_b3 en_b4 en_l3 en_l2 vddqin vttr rsto irq pgood wake dv dd on vin_l4 io18 sda scl vstb 1h pv in4 10f 10f 10f 10f 10f 10f 10f 10f microprocessor control 4.7k v in2 v in1 v shnt fbv cc sw5 fb5 rt pb on wdo irq rst kill en1 en5 en6 sync en2 en3 en4 en7 en8 sw1 sw2 sw3 sw4 fb1 fb2 fb3 fb4 sw6 sw7 sw8 fb6 fb7 fb8 sda scl wdi temp ct 1.02m 1 3.3v 576k v cc v in4 v in3 v in6 v in5 v in8 v in7 715k i033 3.3v 1a 22f 200k 2.2h 215k dram 1.5v 3a arm 1.35v 4a 68f 200k 2.2h gnd 3676 ta04 ltc3375 ltc 3676/ ltc 3676-1 3676fd

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